In a clock frequency divider circuit that generates a clock signal having a lower frequency from an original clock signal having an arbitrary frequency by dividing the frequency of the original clock signal, it is easy to realize a divider circuit whose frequency division ratio, i.e., the ratio of the frequency of the generated clock signal to the frequency of the original clock signal is expressed as “1/M” (M is an integer) (integer frequency divider circuit) by using a counter circuit.
Further, divider circuits capable of performing a frequency division even when the frequency division ratio is a rational number expressed as “N/M” (N is a positive integer and M is a positive integer greater than N) (rational-number frequency divider circuit) have been also proposed (see Patent literatures 1 and 2). According to these related-art techniques, firstly, the value N of the numerator of the frequency division ratio is cumulatively added at each cycle of the input clock signal. Next, if the addition result becomes larger than the value M of the denominator of the frequency division ratio, the value M is subtracted from the cumulative addition result. By performing these operations, and then appropriately masking (thinning out) clock pulses of the input clock signal by referring to the cumulative addition result, the related-art technique realizes a rational-number frequency division.
A specific example of the problem that occurs in the above-described clock frequency divider circuit in the related art is explained with reference to FIGS. 17 and 18. FIG. 17 is an example of semiconductor integrated circuit using a clock frequency divider circuit in the related art. FIG. 18 shows the operation of the clock frequency divider circuit in the related art.
As shown in FIG. 17, a clock frequency divider circuit 200 in the related art generates a clock B by dividing the frequency of a clock S by a rational number based on input frequency division ratio setting. A circuit A (circuit at the other end) and a circuit B (target circuit) communicate with each other through signals Aout and Bout. The signal Aout is output by the circuit A at a timing of a clock A and is received by the circuit B at a timing of a clock B. The signal Bout is output by the circuit B at a timing of the clock B and is received by the circuit A at a timing of the clock A.
FIG. 18 shows clocks B that are generated by dividing the frequency of a clock S at frequency division ratios 11/12 to 4/12. The clocks B can be generated by appropriately masking clock pulses of the input clock S. For example, a clock B corresponding to the frequency division ratio 9/12 is generated by masking three clock pulses at timings T3, T8 and T11 among the twelve clock pulses at the timings T0 to T11 of the clock S.
In this example, assume that the frequency of the clock A is one third of that of the clock S. That is, the frequency division ratio of the clock A to the clock S is 1/3 (=4/12). Note that the phase relation between the clock A and the clocks B makes a full circle in twelve cycles of the clock S. The timings of the twelve cycles, in which the phase relation makes a full circle, are represented by “T0” to “T11”.
Assume also that the circuit A and the circuit B communicate with each other at the timings T0, T3, T6 and T9, which correspond to all the rising edge timings of the clock A. That is, the circuit A outputs the signal Aout and receives the signal Bout at the timings T0, T3, T6 and T9, which are the rising edge timings of the clock A and are the communication timings.
However, the above-described clock frequency divider circuit in the related art does not give any consideration to the communication with circuits using clocks having different frequencies. Therefore, the clock frequency divider circuit in the related art could generate the clock B by masking clock pulses of the clock S at these communication timings. In the case of example shown in FIG. 18, the clock frequency divider circuit generates some of the clocks B by masking a clock pulse of the clock S at the timing T3, T6 and/or T9 among the communication timings.
Specifically, at the timing T3, the clock pulse is masked for the frequency division ratios 9/12 (91), 6/12 (92), and 5/12 (93). Similarly, at the timing T6, the clock pulse is masked for the frequency division ratio 5/12 (94). Similarly, at the timing T9, the clock pulse is masked for the frequency division ratios 7/12 (95), 6/12 (96), and 5/12 (97).